%% Asynchronous Clock Modeling in HDL Coder

% Copyright 2018 The MathWorks, Inc.

%% Guideline ID
% |1.4.4|

%% Severity
% _Recommended_

%% Description
% Most FPGA designs must have more than one clock domain with multiple
% parts of the design operating at various frequencies. You can model the 
% various clock domains in Simulink(TM) by using a pass-through implementation
% for transitioning between different sample rates. These sample rates
% correspond to the clock rates on the FPGA device.
%%
% For an example, open the model |hdlcoder_multi_clock_domain| and then open
% the DUT Subsystem.
load_system('hdlcoder_multi_clock_domain')
set_param('hdlcoder_multi_clock_domain', 'SimulationCommand', 'Update')
open_system('hdlcoder_multi_clock_domain/DUT')
%%
% You see a BlackBox Subsystem that contains a DocBlock,
% which is a text file that corresponds to the Verilog code for a
% passthrough implementation. You can open the DocBlock to see the Verilog code. 
% You see that the output of this Subsystem 
% operates at a different sample rate or is in a clock domain that is 
% different from the sample rate at the input of the Subsystem.
% The Subsystem also contains a commented out path that contains the VHDL
% equivalent of the passthrough implementation. To generate VHDL code,
% uncomment this path and comment out the path that contains the Verilog
% BlackBox implementation.
%%
% To generate Verilog code for this model, run this command:
%
%   makehdl('hdlcoder_multi_clock_domain/DUT')
%
% In the generated Verilog header file, you see the different clock
% domains in the model.
%
% <include>DUT.v</include>
