Index of /nchou/s/matlab-2020b/amd64_rhel6/examples/hdlcoder/main

[ICO]NameLast modifiedSizeDescription
[PARENTDIR]Parent Directory  -  
[ ]AsynchronousClockModelingInHDLCoderExample.m2018-10-05 15:21 1.6K 
[ ]AudioFilterMultipleAXI4StreamChannelsZedBoardExample.m2020-01-20 07:28 16K 
[ ]AvoidAlgebraicLoopErrorsMATLABFunctionBlocksExample.m2019-08-29 10:57 2.6K 
[ ]AvoidConstantBlockConnectionsToSubsystemPortBoundariesExample.m2019-03-21 11:09 2.2K 
[ ]CheckSubsystemforCompatibilitywithHDLCodeGenerationExample.m2018-03-26 13:49 897  
[ ]CheckYourModelForHDLCompatibilityExample.m2018-03-26 13:49 2.1K 
[ ]ConstantFoldingExample.m2020-01-20 07:28 6.2K 
[ ]ConvertDUTToModelReferenceForContinuousTBExample.m2018-11-16 04:57 1.8K 
[ ]CreateDualPortRAMSystemObjectExample.mlx2020-01-30 01:16 3.5K 
[ ]CreateMultirateModelHDLExample.m2019-01-07 13:58 3.6K 
[ ]CreateSimpleDualPortRAMSystemObjectExample.mlx2020-01-30 01:16 3.9K 
[ ]CreateSinglePortRAMSystemObjectExample.mlx2020-01-30 01:16 3.5K 
[ ]CustomizeFloatingPointConfigurationAndGenerateCodeExample.m2018-03-26 13:49 1.7K 
[ ]CustomizeHdlsetupFunctionBasedOnApplicationExample.m2019-01-07 14:26 1.4K 
[ ]CustomizecodingstandardrulesforSimulinktoHDLworkflowExample.m2018-03-26 13:49 1.0K 
[ ]DebugTestPointSignalsWithHDLCoderExample.m2019-12-16 13:46 12K 
[ ]DelayBlocksInTheModelExample.m2018-07-04 11:13 9.4K 
[ ]DescriptionMultiRateIssueHDLExample.m2018-03-26 13:49 2.1K 
[ ]DesigningForEfficientMappingToDSPBlocksOnFPGAExample.m2020-01-20 07:28 3.5K 
[ ]DiscreteFIRSharing.slx2020-01-23 14:17 26K 
[ ]DiscreteFIRSharingExample.m2018-03-26 13:49 2.1K 
[ ]DiscreteFIRStreaming.slx2020-01-23 14:16 26K 
[ ]DiscreteFIRStreamingExample.m2018-03-26 13:49 2.4K 
[ ]DisplayHDLRelatedNondefaultModelParametersExample.m2018-03-26 13:49 563  
[ ]DisplayParametersHDLCodeGenerationExample.m2018-09-28 16:15 1.7K 
[ ]DistPipeInsertionMATLABFunctionBlocksExample.m2019-07-17 15:09 3.1K 
[ ]DistributedPipeliningForVectorSumOfElementsExample.m2019-06-17 09:37 1.6K 
[ ]DualPortRAMWithVectorDataExample.mlx2020-01-30 01:16 3.5K 
[ ]GenerateBlockRAMFromLookupTablesExample.m2019-01-11 13:45 2.9K 
[ ]GenerateHDLCoderForModelsWithBusesExample.m2019-12-16 13:46 8.0K 
[ ]GenerateSimulinkModelFromMultipleVerilogFilesExample.m2019-01-18 12:13 2.5K 
[ ]GenerateSimulinkModelFromSingleVerilogFileExample.m2019-01-18 10:57 1.7K 
[ ]GenerateSimulinkModelFromVerilogFilesWithBlackBoxModulesExample.m2018-06-28 07:24 3.0K 
[ ]GenerateSimulinkModelFromVerilogForVariousOperatorsExample.m2018-08-09 14:34 1.4K 
[ ]GenerateSimulinkModelFromVerilogInfersRAMExample.m2019-01-18 15:48 1.6K 
[ ]GenerateVHDLfortheCurrentModelExample.m2018-03-26 13:49 444  
[ ]GenerateVerilogforaSubsystemWithinaModelExample.m2018-03-26 13:49 656  
[ ]GeneratedParameterizedHDLConstGainExample.m2019-03-21 11:10 1.8K 
[ ]GeneratingHDLCodeForEachSubsystemExample.m2019-01-23 13:17 6.8K 
[ ]GuidelinesForTerminatingCommentingOutBlocksExample.m2019-01-08 11:17 1.4K 
[ ]HDLOptimsMATLABFunctionAndSLBlocksExample.m2019-07-17 15:00 12K 
[ ]ImplicitTypeConversionImportVerilogExample.m2019-01-18 14:47 2.3K 
[ ]InsertUnconditionalTransitionStateHDLCodeExample.m2019-10-10 09:43 1.6K 
[ ]IntroducingOversamplingNFPSubsystemExample.m2019-06-06 10:07 1.3K 
[ ]MapScalarPortsToAXI4MasterInterfacesExample.m2020-01-18 16:29 3.1K 
[ ]ModelBlockAndModelReferencesExample.m2019-11-18 14:20 1.8K 
[ ]MultirateIPCoreGenerationExample.m2018-07-20 11:17 3.7K 
[ ]NativeFloatingPointTargetConfigurationExample.m2018-03-26 13:49 1.3K 
[ ]OpenSimscapeHDLWorkflowAdvisorExample.m2020-02-14 14:33 706  
[ ]OpenTheHDLModelCheckerExample.m2020-01-20 07:28 324  
[ ]OpenTheHDLModelCheckerForASubsystemExample.m2020-01-20 07:28 390  
[ ]OverwriteSavedHDLParametersExample.m2018-03-26 13:49 2.6K 
[ ]ParentModelWithModelReferenceExample.m2019-03-21 11:04 1.3K 
[ ]PeepholeOptimizationsExample.m2019-07-17 20:12 4.1K 
[ ]RAMMappingWithMATLABFunctionBlockExample.m2019-07-17 15:03 4.0K 
[ ]ReadWriteSinglePortRAMExample.mlx2020-01-30 01:16 3.4K 
[ ]Recommendation1UseASingleRateModelExample.m2018-03-26 13:49 1.4K 
[ ]ReduceTheRateDifferentialExample.m2018-03-26 13:49 2.2K 
[ ]ResolveNumericalMismatchWithDelayBalancingExample.m2018-04-02 16:36 4.1K 
[ ]RunWorkflowWithConfigObjectExample.m2018-03-26 13:49 1.5K 
[ ]RunningSum.slx2020-01-23 14:17 31K 
[ ]RunningSum_Custom.slx2020-01-23 14:16 30K 
[ ]RunningSum_OSmanual.slx2020-01-23 14:17 34K 
[ ]SaveAndAccessHDLParametersInStructureExample.m2018-04-11 13:09 785  
[ ]SaveandRestoreHDLRelatedModelParametersExample.m2018-03-26 13:49 1.3K 
[ ]SimpleUpCounterModelHDLCoderExample.m2018-10-16 15:05 684  
[ ]SimulateAndGenerateHDLCodeFloatTypecastBlockExample.m2019-12-16 13:46 1.3K 
[ ]Strategy4UseCustomLatencyExample.m2018-07-04 11:59 1.7K 
[ ]TerminateUnconnectedBlockOutputsExample.m2019-05-02 13:51 1.1K 
[ ]UnableToAllocateDelaysInNFPExample.m2019-06-06 10:01 1.5K 
[ ]UsageOfLogicalBitwiseOperatorExample.m2019-01-11 13:20 2.0K 
[ ]UseDualRateDualPortRAMHDLExample.m2019-01-07 15:52 1.2K 
[ ]UsingMatrixMultiplyExample.m2019-03-14 15:58 2.6K 
[ ]VariantSubsystemChangeSimulationBehaviorExample.m2019-11-18 14:20 2.1K 
[ ]customizehdlsetup.m2018-11-16 05:07 441  
[ ]foreach_subsystem_example1.slx2020-01-23 14:15 24K 
[ ]gm_hdlcoder_constant_subsystem_boundary.slx2020-01-23 14:16 34K 
[ ]gm_hdlcoder_distributed_pipelining_soe.slx2020-01-23 14:17 32K 
[ ]hdlcoder_DUT_discrete.slx2020-01-23 14:17 25K 
[ ]hdlcoder_LUT_BRAM_mapping.slx2020-01-23 14:17 27K 
[ ]hdlcoder_MLFB_avoid_algebraic_loops.slx2020-01-23 14:16 35K 
[ ]hdlcoder_MLFB_share_pipeline.slx2020-01-23 14:15 37K 
[ ]hdlcoder_MLFB_simple_datapath.slx2020-01-23 14:17 28K 
[ ]hdlcoder_RemoveUnconnectedPorts.slx2020-01-23 14:16 26K 
[ ]hdlcoder_audio_filter_multistream.slx2020-01-23 14:16 103K 
[ ]hdlcoder_audio_filter_multistream_init.m2020-01-18 16:29 1.1K 
[ ]hdlcoder_audio_filter_multistream_sw.slx2020-01-23 14:17 46K 
[ ]hdlcoder_audio_filter_multistream_sw_init.m2020-01-18 16:29 126  
[ ]hdlcoder_axi_master.slx2020-01-23 14:17 56K 
[ ]hdlcoder_axi_multirate_sharing.slx2020-01-23 14:16 36K 
[ ]hdlcoder_axi_video_multirate.slx2020-01-23 14:17 30K 
[ ]hdlcoder_block_annotation_HDL_params.slx2020-01-23 14:15 25K 
[ ]hdlcoder_bus_nested.slx2020-01-23 14:17 30K 
[ ]hdlcoder_bus_nested_assignment.slx2020-01-23 14:15 30K 
[ ]hdlcoder_bus_nested_simplified.slx2020-01-23 14:17 31K 
[ ]hdlcoder_chart_ifnelsecond.slx2020-01-23 14:17 32K 
[ ]hdlcoder_combine_operations.slx2020-01-23 14:17 23K 
[ ]hdlcoder_comment_through_out.slx2020-01-23 14:16 34K 
[ ]hdlcoder_constant_simplification.slx2020-01-23 14:16 32K 
[ ]hdlcoder_constant_subsystem_boundary.slx2020-01-23 14:17 28K 
[ ]hdlcoder_distpipe_multiplier_chain.slx2020-01-23 14:16 32K 
[ ]hdlcoder_distributed_pipelining_soe.slx2020-01-23 14:15 25K 
[ ]hdlcoder_divide_parentmodel.slx2020-01-23 14:16 25K 
[ ]hdlcoder_divide_referencedmodel.slx2020-01-23 14:15 23K 
[ ]hdlcoder_dual_rate_dual_port_RAM.slx2020-01-23 14:16 26K 
[ ]hdlcoder_float_typecast_example.slx2020-01-23 14:16 25K 
[ ]hdlcoder_logical_bitwise_operations.slx2020-01-23 14:16 32K 
[ ]hdlcoder_masked_subsystems.slx2020-01-23 14:15 26K 
[ ]hdlcoder_matrix_multiply.slx2020-01-23 14:16 28K 
[ ]hdlcoder_multi_clock_domain.slx2020-01-23 14:16 33K 
[ ]hdlcoder_multiclock.slx2020-01-23 14:16 28K 
[ ]hdlcoder_multiplier_adder_dsp.slx2020-01-23 14:16 54K 
[ ]hdlcoder_multirate_high_differential.slx2020-01-23 14:17 24K 
[ ]hdlcoder_multirate_medium_differential.slx2020-01-23 14:16 24K 
[ ]hdlcoder_nfp_delay_allocation.slx2020-01-23 14:17 24K 
[ ]hdlcoder_nfp_delay_allocation_custom.slx2020-01-23 14:17 25K 
[ ]hdlcoder_product_mixed_types.slx2020-01-23 14:17 22K 
[ ]hdlcoder_protected_model_parent_harness.slx2020-01-23 14:17 27K 
[ ]hdlcoder_ram_mapping_matlab_function.slx2020-01-23 14:17 26K 
[ ]hdlcoder_referenced_model_gain.slx2020-01-23 14:16 24K 
[ ]hdlcoder_remove_redundant_logic.slx2020-01-23 14:17 27K 
[ ]hdlcoder_resolve_delaybalancing.slx2020-01-23 14:17 24K 
[ ]hdlcoder_simple_up_counter.slx2020-01-23 14:16 28K 
[ ]hdlcoder_singlerate.slx2020-01-23 14:16 22K 
[ ]hdlcoder_slow_operation_replacement.slx2020-01-23 14:17 24K 
[ ]hdlcoder_terminateout.slx2020-01-23 14:17 25K 
[ ]hdlcoder_test_points.slx2020-01-23 14:15 38K 
[ ]hdlcoder_testbench_continuous.slx2020-01-23 14:17 24K 
[ ]hdlcoder_variant_subsystem_design.slx2020-01-23 14:17 30K 
[ ]myhdlsetup.m2018-10-23 18:45 2.9K 
[ ]showHdlBlockParams.m2018-09-05 10:12 7.2K