Index of /nchou/s/matlab-2020b/amd64_rhel6/examples/hdlcoder/data

[ICO]NameLast modifiedSizeDescription
[PARENTDIR]Parent Directory  -  
[IMG]Bus_creator_signals_in_bus.png2018-09-24 17:13 21K 
[ ]DUT.v2018-10-05 15:21 1.1K 
[IMG]DiscreteFIRSharing_Arch.png2015-07-04 15:53 16K 
[IMG]DiscreteFIRSharing_HDLBlkProps.png2015-11-06 08:24 13K 
[ ]DiscreteFIRSharing_ImgSrc.pptx2015-07-04 15:53 361K 
[IMG]DiscreteFIRSharing_NoOptims.png2015-11-06 08:24 3.1K 
[IMG]DiscreteFIRSharing_Resource.png2015-11-06 08:24 3.1K 
[IMG]DiscreteFIRSharing_SubSystem.png2015-11-06 08:24 5.7K 
[IMG]DiscreteFIRStreaming_HDLArch.png2015-07-04 15:55 3.8K 
[IMG]DiscreteFIRStreaming_HDLArchNoOptim.png2015-07-04 15:55 3.8K 
[IMG]DiscreteFIRStreaming_HDLBlockProps.png2015-06-30 13:39 23K 
[IMG]DiscreteFIRStreaming_HDLBlockPropsShare.png2015-11-06 08:25 15K 
[ ]DiscreteFIRStreaming_ImgSrc.pptx2015-07-04 15:55 362K 
[IMG]DiscreteFIRStreaming_Resource.png2015-07-04 15:55 5.5K 
[IMG]DiscreteFIRStreaming_ResourceShare.png2015-11-06 08:25 15K 
[IMG]DiscreteFIRStreaming_SubSystem.png2015-06-30 13:39 13K 
[ ]FunkyDrums_48_stereo_25secs.mat2020-01-18 16:29 7.6M 
[ ]Generated.vhd2018-08-30 14:28 541  
[IMG]HDL_DUT_virtual.png2019-01-11 11:28 8.5K 
[IMG]MATLAB_Function_simple_multiplications.png2019-07-11 22:41 3.5K 
[IMG]NG1_implicit.png2019-01-18 14:47 13K 
[ ]NG1_implicit.v2019-01-18 14:47 162  
[IMG]Remove_Redundant_Logic.png2019-07-17 20:12 3.1K 
[IMG]Remove_Unconnected_Ports.png2019-07-17 20:12 36K 
[IMG]Subsystem_Foreach_VHDL.png2016-12-19 10:07 6.2K 
[IMG]Synth_report_dspsubsys1.png2020-01-20 07:28 17K 
[IMG]Synth_report_dspsubsys2.png2020-01-20 07:28 18K 
[ ]Top.vhd2018-10-09 18:25 1.4K 
[ ]VerilogOperators.v2018-06-18 12:37 679  
[IMG]axi_master_ipcore.png2020-01-18 16:29 125K 
[IMG]axi_master_read_waveform.png2017-07-21 11:06 50K 
[ ]blackboxtop.v2018-06-28 07:24 412  
[IMG]blackboxtopmodule.v.png2018-06-28 07:25 15K 
[ ]comparator.v2019-01-18 10:58 330  
[IMG]comparator.v.png2019-01-18 10:58 13K 
[IMG]compare_error_validationmodel.png2017-12-13 10:39 18K 
[IMG]compare_zeroerror_validationmodel.png2017-12-13 10:39 18K 
[ ]conditionalcomb.v2018-06-27 16:00 357  
[IMG]cpe_MLFB_MATLAB_Function.png2019-07-11 22:41 45K 
[IMG]distpipe_MLFB_MATLAB_Datapath1.png2019-07-11 22:41 25K 
[IMG]distpipe_MLFB_MATLAB_Datapath2.png2019-07-11 22:41 23K 
[IMG]distpipe_MLFB_MATLAB_Function1.png2019-07-11 22:41 23K 
[IMG]distpipe_MLFB_MATLAB_Function2.png2019-07-11 22:41 94K 
[IMG]distributed_pipelining_report_soe_vectors.png2018-09-04 10:07 65K 
[ ]example.v2018-06-18 11:00 385  
[IMG]example.v.png2019-01-18 12:13 26K 
[ ]example1.v2019-01-18 12:13 398  
[ ]example2.v2018-06-18 11:00 208  
[IMG]example_top.v.png2018-06-18 12:51 12K 
[IMG]filter_select_block_parameters.png2020-01-20 07:28 21K 
[IMG]foreach_subsystem_equivalent.png2016-12-19 10:07 39K 
[IMG]gm1_hdlcoder_nfp_delay_allocation.png2017-06-03 19:40 4.9K 
[IMG]gm1_hdlcoder_nfp_delay_allocation1.png2017-05-25 08:37 4.0K 
[IMG]gm_combine_operations.png2017-12-26 11:52 4.7K 
[IMG]gm_constant_folding.png2018-01-03 14:39 41K 
[IMG]gm_distpipe_mult_chain1.png2019-07-11 22:42 50K 
[IMG]gm_distpipe_mult_chain2.png2019-07-11 22:42 59K 
[IMG]gm_foreach_subsystem.png2017-03-28 09:44 36K 
[IMG]gm_foreach_subsystem_instance.png2017-03-28 09:44 26K 
[IMG]gm_hdlcoder_nfp_delay_allocation.png2017-06-03 19:40 6.2K 
[IMG]gm_hdlcoder_nfp_delay_allocation_custom.png2018-07-02 11:14 4.1K 
[IMG]gm_hdlcoder_test_points.png2018-01-09 16:13 63K 
[IMG]gm_matlab_datapath_MLFB_inside.png2019-07-11 22:41 8.5K 
[IMG]gm_ram_mapping_matlab_datapath.png2019-07-11 22:41 37K 
[IMG]gm_strength_reduction.png2017-12-26 11:51 10K 
[IMG]guideline_synthesis_lut_noram.png2018-11-20 11:10 18K 
[IMG]guideline_synthesis_lut_ram.png2018-11-20 11:10 19K 
[IMG]hdl_check_report_mixed_types.png2017-06-05 15:51 17K 
[IMG]hdlcoder_gm_high_rate_diff.png2017-10-12 11:36 47K 
[IMG]hdlcoder_gm_medium_rate_diff.png2017-10-12 12:41 46K 
[IMG]hdlcoder_gm_single_rate.png2017-10-12 11:48 33K 
[IMG]hdlcoder_high_rate_diff.png2017-10-12 11:36 37K 
[IMG]hdlcoder_makehdl_high_rate_diff.png2017-10-12 11:36 34K 
[IMG]hdlcoder_makehdl_medium_rate_diff.png2017-10-12 12:41 157K 
[IMG]hdlcoder_makehdl_single_rate.png2017-10-12 11:48 113K 
[IMG]hdlcoder_medium_rate_diff.png2017-10-12 12:41 37K 
[IMG]hdlcoder_nfp1_delay_allocation.png2017-06-03 19:40 13K 
[IMG]hdlcoder_nfp2_delay_allocation.png2017-06-03 19:40 12K 
[IMG]hdlcoder_nfp_delay_allocation.png2017-06-03 19:40 11K 
[IMG]hdlcoder_nfp_delay_allocation_oversampling.png2017-06-03 19:40 15K 
[IMG]hdlcoder_single_rate.png2017-10-12 11:48 34K 
[IMG]hdlmodelchecker_sfir_single.png2019-10-16 10:38 47K 
[IMG]hparams_fields.png2018-04-11 13:09 13K 
[IMG]if_else_chart_verilog.png2019-09-04 11:07 16K 
[IMG]if_only_chart_verilog.png2019-09-04 11:07 13K 
[IMG]implicit_top.png2019-01-18 14:47 9.4K 
[ ]implicit_top.v2019-01-18 14:47 267  
[IMG]intel_fpga_dsp_arch_guideline.png2019-11-18 14:20 50K 
[ ]intelip.v2018-06-28 07:25 208  
[IMG]intelipmodule.v.png2018-06-28 07:25 5.3K 
[IMG]line_buffer_ml_code.png2019-07-11 22:41 16K 
[IMG]mult_chain_ml_code.png2019-07-11 22:42 8.5K 
[IMG]nfp_latency_strategy_model.png2017-05-25 08:37 31K 
[IMG]oversampling_factor_config_params.png2017-05-25 08:37 32K 
[IMG]persistent_MLFB_alg_loop.png2019-08-29 10:45 11K 
[IMG]ram_mapping_mappersistentvars_disabled.png2019-07-11 22:41 10K 
[IMG]ram_mapping_mappersistentvars_enabled.png2019-07-11 22:41 9.7K 
[ ]round_constant.v2019-01-18 14:47 123  
[IMG]scope_sw_model_multiple_streamchannels.png2020-01-18 16:29 63K 
[IMG]seq_comb.v.png2018-06-28 07:25 28K 
[ ]sequentialexp.v2018-06-27 16:00 335  
[IMG]set_target_device_synth_tool_mutiple_streamchannels.png2020-01-18 16:29 39K 
[IMG]set_target_frequency_mutiple_streamchannels.png2020-01-18 16:29 23K 
[IMG]set_target_interface_multiple_streamchannels.png2020-01-18 16:29 106K 
[IMG]set_target_reference_design_multiple_streamchannels.png2020-01-18 16:29 34K 
[IMG]sharing_MATLAB_Datapath_across.png2019-07-11 22:41 34K 
[IMG]sharing_MATLAB_Datapath_inside.png2019-07-11 22:41 36K 
[IMG]sharing_MLFB_MATLAB_Datapath.png2019-07-11 22:41 51K 
[IMG]sharing_MLFB_MATLAB_Function.png2019-07-11 22:41 49K 
[ ]simple_dual_port_ram.v2019-01-18 15:49 604  
[IMG]simple_dual_port_ram.v.png2019-01-18 15:49 23K 
[IMG]sw_interface_model_multiple_streamchannels.png2020-01-18 16:29 117K 
[IMG]system_architecture_audio_multiple_streamchannels.png2020-01-18 16:29 73K 
[IMG]target_platform_table_axi_stream.png2018-07-13 10:43 37K 
[IMG]target_platform_table_axi_video.png2018-07-13 10:43 44K 
[IMG]test_points_generated_code.png2017-06-02 16:22 12K 
[IMG]test_points_hdl_workflow.png2018-01-09 16:13 22K 
[IMG]test_points_ip_core_report.png2018-01-09 16:13 58K 
[IMG]test_points_report.png2018-01-09 16:13 43K 
[IMG]testpoint_dut_ip_core_interface.png2018-01-09 16:13 15K 
[IMG]testpoint_software_interface_model.png2018-01-09 16:13 43K 
[IMG]verilog_operators.v.png2018-06-18 12:37 24K 
[IMG]vivado_project_multiple_streamchannels.png2020-01-18 16:29 111K 
[ ]weightingTable.mat2020-01-18 16:29 11K 
[IMG]xilinx_fpga_dsp_arch_guideline.png2019-11-18 14:20 33K 
[IMG]zedboard_setup_multiple_streamchannels.png2020-01-18 16:29 556K