Module Compiler 1998.02

Release Notes

The following release notes apply to the 1998.02 release of Synopsys Module Compiler.

Improvements to Input Processing

• Improved parsing of GUI data entry fields. White space is ignored and null fields are now accepted.
• Improved error message associated with having a carrysave operand in a sequential feedback loop.
• The width of signals can now be declared more directly. In addition to the [width-1:0] style, [width] is now supported. For example, the following are both 8 bit wires:

  wire [7:0] OldStyle;

  wire [8]   NewStyle;

Improvements in Technology Library Support

• Wireload tables whose last fanout entry is a multiple of 64 are now supported correctly.
• License checking is now performed if the .db technology library is protected by a license.
• Fixed bug in reading .db libraries with certain port naming styles.
• Fixed bad logic bug related to cells with timing arcs from one output to another output.

Optimization Improvements

• Eliminated large negative jumps in optimization related to some libraries with resistance. The bug occurred mostly in the logicmin3 step of optimization.
• Fixed optimization problems that caused poor run time in some cases and even an infinite loop in one case.
• Improved optimization run time.

Miscellaneous Improvements

• Eliminated segmentation fault that occurred when both pipeline and edif output were on.
• Long comment lines in VHDL are now written correctly.
• Fixed bug associated with pipestall and multiple groups. The pipestall attribute was not initialized properly for new groups.

Documentation Update

• All Module Compiler documentation is now available in Adobe's Portable Document Format (PDF) and in Postscript as well. The User Guide, Reference Manual, and Module Compiler Express User Guide are all available. The documentation directory is located at $MCDIR/doc.
• You will need the Adobe Acrobat Reader to view the documents. You can download a free copy of the Adobe Acrobat Reader at http://www.adobe.com/acrobat/readstep.html.

Known Limitations

• Cells in the technology library that have timing arcs from one output to another output are currently not supported. These cells are marked as unusable.
• Cells that have bussed pins are currently not supported. This limitation affects physical memories in particular since they are frequently modeled with bussed pins.
• Physical memories are currently not supported by Module Compiler. For designs that have physical memories, the current solution is to make the IO of the memory IO of the MC module. Then instantiate the physical memory and the MC module at the next level up in the design hierarchy (outside of MC). For designs with netlist-based memories, asyncRF() and syncRF() are still fully supported.