#! /bin/csh -f
#**************************************************#
#* Analyze the synthesizable model                *#
#* Analyze the test bench                         *#
#* Bring up the debugger and waveform display     *#
#* sim.scr is simulation command file which       *#
#* gets executed when the debugger comes up       *#
#**************************************************#

vhdlan types-pack.vhd
vhdlan s2p-seq.vhd
vhdlan tb_s2p-seq.vhd
vhdldbx -i sim.scr cfg_tb_ser_par
