Index of /nchou/p/cad/maxplus2/simlib/composer/alt_syn/verilog

	Name	Last modified	Size	Description
	Parent Directory		-
	a_gnd.v	1994-11-22 19:35	488
	a_tri.v	1994-11-22 19:30	807
	a_vcc.v	1994-11-22 19:34	487
	and2.v	1994-11-22 19:10	775
	and3.v	1994-11-22 19:10	848
	and4.v	1994-11-22 19:10	920
	and6.v	1994-11-22 19:11	1.0K
	and8.v	1994-11-22 19:11	1.2K
	and12.v	1994-11-22 19:12	1.5K
	dff.v	1994-11-22 19:33	1.6K
	inv.v	1994-11-22 19:31	703
	latch.v	1994-11-22 19:32	1.1K
	nand2.v	1994-11-22 19:13	774
	nand3.v	1994-11-22 19:14	852
	nand4.v	1994-11-22 19:15	922
	nand6.v	1994-11-22 19:18	1.0K
	nand8.v	1994-11-22 19:18	1.2K
	nand12.v	1994-11-22 19:20	1.5K
	nor2.v	1994-11-22 19:25	775
	nor3.v	1994-11-22 19:25	848
	nor4.v	1994-11-22 19:26	920
	nor6.v	1994-11-22 19:27	1.0K
	nor8.v	1994-11-22 19:28	1.2K
	nor12.v	1994-11-22 19:29	1.5K
	or3.v	1994-11-22 19:20	846
	or4.v	1994-11-22 19:20	918
	or6.v	1994-11-22 19:21	1.0K
	or8.v	1994-11-22 19:23	1.2K
	or12.v	1994-11-22 19:23	1.5K
	soft.v	1994-11-22 19:34	868
	tff.v	1994-11-22 19:32	1.9K
	xor2.v	1994-11-22 19:29	776