vhdl_lib                                           Associates a VHDL library
                                                   name, a data type, and a
                                                   design unit type with the
                                                   Verilog library to be
                                                   compiled, or displays the
                                                   current settings.
 [ library_name ]
 [ -datatype                data_type ]              std_logic, std_ulogic
                                                     /std_logic
 [ -designunit              design_unit_type ]       entity, configuration
                                                     /entity
