<VERIFYLIBRARY 
"VERIFY LIBRARY 

Checks the values of the technology data for consistency and completeness.


Syntax

V*ERIFY L*IBRARY 
[T*ECHNOLOGY | ALL*MODELS 	
|M*ODEL modelRegExpr,... ] 	
[W*ARNINGLIMIT limit] 	
[E*RRORLIMIT limit] ;


Arguments

TECHNOLOGY
Specifies that the technology data (layers, design rules, and so on) in the database is to be verified.

ALLMODELS, MODEL modelRegExpr,... 
MODEL selects particular library models for verification; ALLMODELS verifies all library models. Default: all models

WARNINGLIMIT limit
Specifies the maximum number of warnings to report before stopping. Default: the value of Verify.WarningLimit

ERRORLIMIT limit
Specifies the maximum number of errors to report before terminating verification. Default: the value of Verify.ErrorLimit


Description

VERIFY LIBRARY checks cell model electrical data, consistency of substitutable cell models, cell placement site type usage, and cell pin characteristics. VERIFY LIBRARY includes checks for the most likely user and translator errors in addition to more serious errors.

Technology Data

Technology data must use defined and consistent values, and proper units based on user-specified ranges for spacing, widths, via geometries, and so on.

The total number of routing and pin layers must be less than 31. Exactly one default via must exist for all pairs of adjacent routing layers. Via and layer names must not be duplicated.

Default via generation rules must exist for all pairs of adjacent routing layers, including turn-vias for each routing layer. Each masterslice layer containing a macro port must have a default generation rule for vias to the first routing layer. When creating a via rule, you can create a default via rule that covers all vias other than those whose widths are explicitly defined by omitting the WIDTH statement when creating the via rule. 

Each defined via must have a cut layer, or a warning is generated.

The X size or Y size of each GCell must be at least as large as the smallest via-to-line spacing in that direction on each layer. VERIFY reports a problem if a GCell falls within the track grid; otherwise, it reports a warning.

Model Size and Sites

Each site description referenced by a model in the library must have at least one site instance in the array. The combination of site descriptions and orientations for a macro must exist in the array for at least one of the macro's symmetries. 

For example, the following case generates an info: a macro needs site A with N orientation and site B with FS orientation, sites A and B are not symmetric about X, and sites A and B only appear in the array having the same orientation.

Each model must contain at least one site placement requirement. The model outline (SIZE) must equal the bounding box of required sites. A warning is generated if the model SIZE is not positive (if width and height are not greater than 0).

Model Pin

Only power, ground, or mustjoin pins can follow the first power or ground pin. EEQ model pins must match in name, direction, use, and shape. Mustjoin connections and LEQ pin sets must be identical.

LEQ model schematic pins must match in name, direction, and use. LEQ pin sets must be identical. Power and mustjoin pins are not schematic pins.

Model names and library pin names within a model must be unique. LEQ pins in an EEQ or LEQ model must be declared contiguously. LEQ pins in an EEQ or LEQ model cannot be defined in a mustjoin ring.

Model Pin Ports

Ports must have geometries. If a model pin has no ports, a warning is generated. Ports and obstructions must be orthogonal to the X and Y axes. Ports of different pins must not have shorts unless it is an LEQ pin for this pin.

For any port not on a routing layer, a via must be defined which connects to a routing layer. 

A warning is generated if a pin has no ports that can be wired in a straight path to the edge of the model using at most one via. A warning message is generated if the only such path is wrong-way. For any library port covered by an obstruction, the verifier allows a via to connect to an available routing layer. Verify.Allow.PinInObstruction has no effect on library verification.

A warning is generated for any pin with no ports that cover at least one routing grid point.

Model Pin Shape

For each feedthrough or abutment pin port, the union of the port geometries must intersect the macro site boundary rectangle to form one or more pairs of boundary edges in such a way that, for each pair, the two edges that are the same width are aligned on opposite sides of the macro. 

Abutment pins must be on the same routing layer. Feedthrough pins can be on the masterslice. Each of these edges must belong to a wire. Vias are only allowed at the edge if a wire is defined there also.

For each abutment pin port, the rectangular paths connecting each pair of boundary edges must be completely covered by the geometries for the port.

For any feedthrough, abutment, or ring pin that has more than one port, a warning is generated. For any feedthrough or abutment pin port that has a geometry extending past the macro site boundary rectangle, a warning is generated. For any feedthrough pin port containing more than one pair of boundary edges, a warning is generated.

During the run, VERIFY displays status messages and a summary of generated warnings and problems in the message window. All warnings and problems detected are logged in the database as infos. To obtain a more detailed description of the problem, run DESCRIBE MESSAGE using the message number from the message window or report file, and type ``?''.


Environmental Variables

Verify.Errorlimit 
INTEGER [0, 10000000] - Default: 1000 - NOVICE 
Number of errors of each type at which verification is terminated.

Verify.Technology.Max.FeatureSize 
INTEGER [0, 1000000] - Default: 10000 - NOVICE 
Maximum reasonable dimension of technology data (spacings, widths, vias).

Verify.Technology.Min.FeatureSize 
INTEGER [0, 1000000] - Default: 0 - NOVICE 
Minimum dimension of technology data (spacings, widths, vias).

Verify.Warninglimit 
INTEGER [0, 10000000] - Default: 50 - NOVICE 
Number of warnings of each type at which info recording is stopped.


Example

VERIFY LIBRARY MODEL INV21 , NAND35 ;


Related Commands

VERIFY CONNECTIVITY verifies connections.

VERIFY GEOMETRY verifies geometry.

FIND INFO interactively locates violations.

REPORT INFO generates a report on infos.
"

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	<Header "Verify Library Command Help">
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