<REPORTCONSTRAINTS 
"REPORT CONSTRAINTS           

Generates a report that shows how well the current design meets the timing and wired-logic distance constraints for the design.


Syntax

R*EPORT CO*NSTRAINTS 
[S*HORT | DET*AILED] 	
[D*ELAYMODEL {C | PI | TABLE}] 	
[C*DERATE factor] 	
[I*DERATE factor] 	
[F*ILENAME outputFile] 	
[L*IMIT lineLimit] ;


Arguments

SHORT | DETAILED
Gives either a short report that shows total number of constraints and the number of constraints met or an expanded report that includes the target and actual delay limits for all constraints. Default: If you do not specify short or detailed, this command reports only constraints that have not been met.

DELAYMODEL {C | PI | TABLE} 
Selects the timing delay model to determine the parasitics as part of the delay calculations: C, PI, or TABLE. Default: Value of Timing.Delay.Model.If your design contains only placement and no routing, the C model is used regardless of the setting of this variable.

CDERATE factor
Derating factor for cell delays, a real value between 0.0 and 1000000.0. This derating factor lets you experiment with scaling component delays without having to specify different sets of delays in multiple runs. Default: Value of Timing.Cderate 

IDERATE factor
Derating factor for interconnect delay, a real value between 0.0 and 1000000.0. This derating factor lets you experiment with scaling interconnect delays without having to specify different sets of delays in multiple runs. Default: Value of Timing.Iderate 

FILENAME outputFile
Specifies the file in which to store the report. Default: constr.rpt

LIMIT lineLimit
Maximum number of lines for the report. Default: Maximum integer in the system


Description

Note: REPORT CONSTRAINTS is included with the Timing Assurance and ECL Technology options. It generates a constraints report showing how well the current design meets timing and wired-logic distance constraints, as specified by ASSURE ESTCAP or by DEF constraints.

Note: If you set Timing.Delay.Model to C or PI for ASSURE ESTCAP, you should also set the timing model variable to C when running REPORT CONSTRAINTS. If you set Timing.Delay.Model to TABLE, you should also set the timing model variable to TABLE for REPORT CONSTRAINTS.

DEF constraints have the following form:

[ operand value... 
| WIREDLOGIC net MAXDIST target actual 
]...

operand = 
{NET netName 	
| PATH comp fromPin comp toPin 	
| SUM (operand,...)  }

value = 
{RISEMIN target actual 	
| RISEMAX target actual 	
| FALLMIN target actual 	
| FALLMAX target actual}

REPORT CONSTRAINTS reports timing constraints for net constraints, path constraints, and the sum of other operands. RISEMIN, RISEMAX, FALLMIN, and FALLMAX correspond to minimum and maximum delays for rising and falling signals at the input to the PATH. 

For each constraint, REPORT CONSTRAINTS provides

- Target and actual values. Target value is the value of the original constraint. If there is no routing, the actual value is the calculated or estimated value for the specified delay model. 

A constraint is met only if the delay is between the MIN and MAX delay. 

- Distance constraints and actual values for each constrained wired-logic net.
REPORT CONSTRAINTS provides the delays according to the values you specify for fromPin and toPin in the Constraints section of DEF.

- Intrinsic delay is the delay between an input and output pin pair of a macro when the output pin is not connected to a net (load).

- Extra Source Gate Delay (ESGD) is the additional delay between the same input and output pin pair when the output pin is connected to a net and is driving that net. 

- Propagation delay (PD) is the delay between an output pin of one macro to the input pin of another macro.

The SHORT report shows two numbers: the total number of constraint conditions, and the number of those conditions that are met by the current design. The default report (neither DETAILED nor SHORT) also shows the timing data for those operands that do not meet their constraints. The DETAILED report shows data for all operands that have constraints.

Unless an output file is specified, REPORT CONSTRAINTS writes to the default report file constr.rpt. If LIMIT is used, the report generator terminates when the number of lines in the report reaches the specified limit.

CDERATE and IDERATE set values for the device and interconnect delay derating factors, temporarily overriding the values set by Timing.Cderate and Timing.Iderate. If you chose the TABLE option for DELAYMODEL, CDERATE and IDERATE will not override the derating factors when the constraint report is generated.

To avoid a memory full problem, set USE for the power and ground nets in the DEF file, or use the CHANGE NET command. The following example uses gnd and vdd as net names:

  CHANGE NET gnd USE ground 
  CHANGE NET vdd USE power


Environmental Variables

Input.Threshold.Fall 
REAL [0.001, 0.999] - Default: 0.5 NOVICE/EXPERT 
Normalized threshold value for detecting a falling voltage transition.

Input.Threshold.Rise 
REAL [0.001, 0.999] - Default: 0.5 NOVICE/EXPERT 
Normalized threshold value for detecting a rising voltage transition.

Timing.Default.KFactor 
REAL [0.0, 100000.0] - Default: 1.0 - NOVICE 
This variable has an effect only if you chose the C model for Timing.Delay.Model. The value is the default K-factor used for delay calculations if the intrinsic delays of a cell are not defined or are all 0.0 in your LEF file. If you set this value to 0.0, intrinsic delays are ignored.

Timing.Delay.Model 
STRING {C | PI | TABLE} - Default: PI NOVICE/EXPERT 
Model used (as part of the delay calculation) to calculate the load admittance seen by a driving pin.

Timing.Capacitance.Model 
STRING {PP | VDMF} - Default: ''PP'' - NOVICE 
Model used to calculate wire capacitance: Parallel Plate model or Van Der Meijs and Fokkema fringing model.

Timing.CDerate 
REAL [1.0E-38, 1000000.0] - Default: 1.0 - NOVICE 
Default multiplier applied to cell intrinsic delays. This derating factor lets you experiment with scaling component delays without having to specify different sets of delays in multiple runs.

Timing.Environment.Tablename 
STRING - NOVICE/EXPERT 
You can use this variable to specify an operating environment for the design. The operating environment determines the set of timing tables selected for each timing arc.

Timing.IDerate 
REAL [1.0E-38, 1000000.0] - Default: 1.0 - NOVICE 
Default multiplier applied to load-dependent and interconnect delays. This derating factor lets you experiment with scaling interconnect delays without having to specify different sets of delays in multiple runs.

Timing.Nominal.Slew.Fall 
REAL [0.0, 10.0] - Default: 0.0 - NOVICE/EXPERT 
Assumed slew rate for falling signals at all primary inputs.

Timing.Nominal.Slew.Rise 
REAL [0.0, 10.0] - Default: 0.0 - NOVICE/EXPERT 
Assumed slew rate for rising signals at all primary inputs.

Timing.Report.Constraints.Ignore.Min.Value
BOOLEAN - Default: TRUE
The software does not check if the ''min'' target constraint meets the
target value.

Timing.Report.Delay.Ignore.RC.Zero
BOOLEAN - Default: TRUE
Suppresses warning messages when the RC value for an src sink pin pair is 0.

Timing.Report.Ignore.Loops.Inconnected.Points
BOOLEAN - Default: TRUE
Net wires are not checked for loops or unconnected pins.

Timing.Reports.HigherPrecision 
BOOLEAN - Default: false - NOVICE 
If true, all timing reports report delays to six decimal places.

Timing.STD.Transtime.Rise.{Min |Typ |Max} 
REAL [0.0, 1.0] - Default: 0.0 - EXPERT 
Specifies the standard RISE ramp (transition) time at input pins.

Timing.STD.Transtime.Fall.{Min |Typ |Max} 
REAL [0.0, 1.0] - Default: 0.0 - EXPERT 
Specifies the standard FALL ramp (transition) time at input pins.

Timing.Report.Portname.Convert 
BOOLEAN -Default: false -NOVICE/ EXPERT 
If true all instances which start with the value of ''TIMING.REPORT.PORTNAME.PREFIX'' will treated as IO pin instances. The piname will be extracted by removing the prefix from the instance name. Only the pinname will appear in the constraints file, no component name.

Timing.Report.Portname.Prefix 
STRING - Default: ''TDPin_'' - NOVICE/EXPERT 
The prefix which is used for IO pin instances. This variable is used together with the Timing.Report.Portname.Convert variable.


Example 1

REPORT CONSTRAINTS ;

REPORT CONSTRAINTS 
FILENAME demochip.rpt 
DETAILED CDERATE .75 IDERATE 2 ;
#Design Name : rpuAsic 
#Resistance Units : 1 ohms 	
#Capacitance Units : 1 pico farads 	
#Time Units : 1 nano seconds 	
# Syntax: [ <operand> <value> ...]... 	
# | WIREDLOGIC <net> MAXDIST <target> <actual> 
# operand ::= NET <net> 	
# | PATH <comp> <fromPin> <comp> <toPin> 	
# | <operand>,... SUM 	
# value ::= [ RISEMIN <target> <actual> ] | 	
# [ RISEMAX <target> <actual> ] | 	
# [ FALLMIN <target> <actual> ] | 	
# [ FALLMAX <target> <actual> ] 
# TIMING.ADMITTANCE.MODEL = PI 	
# TIMING.CAPACITANCE.MODEL = PP 

PATH|rp|Decoder|mod011127 
     A 		|rp|Decoder|mod011127
 		      Y 
PATH |rp|Decoder|mod011127 
          Y 	    |rp|Decoder|mod011126
 			   A 
PATH |rp|Decoder|mod011126 				
        A 	    |rp|Decoder|mod011126
 			 Y 
PATH |rp|Decoder|mod011126 		 		
        Y 	     |rp|Decoder|mod011125
 			   A 
PATH |rp|Decoder|mod011125 		 		
        A 	   |rp|Decoder|mod011125
 			  Y 
. . .

SUM 
RISEMIN 2.601 4.999 RISEMAX 7.544 5.002 		
FALLMIN 2.296 4.629 FALLMAX 7.105 4.631
TOTAL 1
MET 1 
ILLEGAL 0


Related Commands

ASSURE ESTCAP generates timing constraints based on estimated net capacitances.

DELAY is an interactive calculator for propagation delays.

REPORT DELAY generates a report that shows interconnect delay limits for each net in the design and cell delay limits for each cell that has a timing relation.

REPORT RC reports resistance and capacitance parameters used in delay calculation.
"

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	<Header "Report Constraints Command Help">
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