Pixel Stream Aligner

Align two streams of pixel data

  • Library:
  • Vision HDL Toolbox / Utilities

Description

The Pixel Stream Aligner block synchronizes two pixel streams by delaying one stream to match the timing of a reference stream. Many Vision HDL Toolbox™ algorithms delay the pixel stream, and the amount of delay can change as you adjust algorithm parameters. You can use this block to align streams for overlaying, comparing, or combining two streams such as in a Gaussian blur operation. Connect the delayed stream to the refPixel and refCtrl input ports, and the earlier stream to the pixel and ctrl input ports.

This waveform diagram shows the input streams, pixelIn and refPixelIn, and their associated control signals. The reference input frame starts later than the pixelIn frame. The output signals show that the block delays pixelIn to match the reference stream, and that both output streams share control signals. There is a short latency between the input refCtrl and the output refCtrl. In this simulation, to accommodate the delay of four lines between the input streams, the MaxNumberOfLines must be set to at least 4.

Ports

This block uses a streaming pixel interface with a pixelcontrol bus for frame control signals. This interface enables the block to operate independently of image size and format. All Vision HDL Toolbox blocks use the same streaming interface. The block accepts and returns a scalar pixel value and a bus that contains five control signals. The control signals indicate the validity of each pixel and its location in the frame. To convert a frame (pixel matrix) into a serial pixel stream and control signals, use the Frame To Pixels block. For a full description of the interface, see Streaming Pixel Interface.

Input

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Single image pixel of a pixel stream, specified as a vector of three values representing R'G'B' or Y'CbCr, or a scalar value representing intensity. The block delays this pixel stream to match the control signals of the reference stream, refPixel. Therefore, pixel must be the earlier of the two streams.

double and single data types are supported for simulation, but not for HDL code generation.

Data Types: fixed point | int8 | int16 | int32 | uint8 | uint16 | uint32 | Boolean | double | single

Control signals associated with the pixel stream, specified as a pixelcontrol bus that contains five signals. The signals describe the validity of the pixel and its location in the frame. For more information, see Pixel Control Bus.

Data Types: bus

Single image pixel of a pixel stream, specified as a vector of three values representing R'G'B' or Y'CbCr, or a scalar value representing intensity. The block delays the pixel input stream to match the reference control signals. Therefore, refPixel must be the later of the two streams. The reference data and its control signals pass through the block with a small delay.

double and single data types are supported for simulation, but not for HDL code generation.

Data Types: fixed point | int8 | int16 | int32 | uint8 | uint16 | uint32 | Boolean | double | single

Control signals associated with the pixel stream, specified as a pixelcontrol bus that contains five signals. The signals describe the validity of the pixel and its location in the frame. For more information, see Pixel Control Bus.

The block uses these control signals for the aligned output stream.

Data Types: bus

Output

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Single image pixel, returned as a vector of three values representing R'G'B' or Y'CbCr, or a scalar value representing intensity. The data type is the same as the data type of the pixel input stream.

Single image pixel, specified as a vector of three values representing R'G'B' or Y'CbCr, or a scalar value representing intensity. The data type is the same as the data type of the refPixel input stream. This stream is passed through the block unchanged.

The input refCtrl signals pass through the block with a small delay.

Parameters

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Choose a power of two that accommodates the number of active pixels in a horizontal line. If you specify a value that is not a power of two, the block uses the next largest power of two. The block implements a circular buffer of 2M pixels, where M is MaxNumberOfLines + log2(LineBufferSize).

The block implements a circular buffer of 2M pixels, where M is MaxNumberOfLines + log2(LineBufferSize), and a line address buffer of MaxNumberofLines locations. The circular memory stores the earlier input lines until the reference control signals arrive. The line address buffer stores the address of the start of each line. When the reference control signals arrive, the block uses the stored address to read and send the delayed line. This parameter must accommodate the difference in timing between the two input streams, including internal latency before the block reads the first line. During simulation, the block warns when an overflow occurs. To avoid the overflow condition, increase MaxNumberofLines. The delay between streams cannot exceed an entire frame.

Algorithms

The block stores the data from the pixel port to a circular buffer, and reads the lines out to align with the reference control signals. The block also stores the address of the start of each line. To match the added processing delay of the buffer data path, the block delays the reference pixel data and control signals for around 10 cycles.

The RAM Circular Buffer is a memory of 2M pixels, where M is MaxNumberOfLines + log2(LineBufferSize). The Line Address Buffer has MaxNumberOfLines locations. If the number of ctrl.Hstart assertions before the first refCtrl.Hstart assertion is greater than the size of the Line Address Buffer, the block overwrites both buffers and corrupts your output. In this diagram, MaxNumberOfLines is four, so there are four locations to store a line address in the buffer. The diagram also shows a single location to store ctrl.Vstart. The delay between the two streams must be less than the time between frame starts.

Extended Capabilities

Introduced in R2017a