Variant Subsystem, Variant Model

Template subsystem containing Subsystem blocks or Model blocks as Variant choices

Library:
Simulink / Ports & Subsystems
HDL Coder / Ports & Subsystems

Description

The Variant Subsystem block can have at most one active choice for simulation. The Variant Subsystem block is a template preconfigured to contain two Subsystem blocks to use as Variant Subsystem choices.

A Variant Subsystem block can contain a mixture of Subsystem and Model blocks as Variant systems. This can also include Inport, Outport, and Connection Port blocks. There are no drawn connections inside the Variant Subsystem blocks.

A Variant Subsystem block with Model blocks as choices, is called Variant Model block.

Each Variant system is associated with a Variant control that is created in the global workspace. The Variant control determines which Variant system is active. The Variant control can be a condition expression, a Simulink.Variant object specifying a condition expression, or a default Variant. The Variant control that evaluates to true determines the active Variant.

When you select the Specify output when source is unconnected option in the Outport block that is in a Variant Subsystem block, you can specify a non-ground value as its output.

Note

You must specify the correct data type in the Signal Attributes section of the Outport block dialog box.

Ports

During simulation, Simulink^® disables the inactive ports in a Variant Subsystem block.

Input

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`In_1` — Input port corresponding to root-level Inport blocks contained in Variant Subsystem
same data types accepted by Inport blocks

Each Subsystem or Model block contained within a Variant Subsystem represents one Variant system. If the inport names on a Variant system are a subset of the inport names used by the Variant Subsystem container block, then Variant system blocks can have different numbers of inports than the Variant Subsystem block has.

Output

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`Out_1` — Output port corresponding to root-level Outport blocks contained in Variant Subsystem
same data types accepted by Outport blocks

Each Subsystem or Model block contained within a Variant Subsystem represents one Variant system. If the outport names on a Variant system are a subset of the outport names used by the Variant Subsystem block, then Variant system blocks can have different numbers of outports than the Variant Subsystem block has.

Parameters

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`Variant control mode` — Name of the Variant control mode
`Expression` (default) | `Label`

To choose the active Variant based on the evaluation of the Variant conditions, use the Expression mode else select Label mode. When you select the Variant control mode as Label, the Label mode active choice option is available. In Label mode, Variant control need not be created in the global workspace. You can select an active Variant choice from Label mode active choice options.

When you select Label mode, the Variant badge indicates the change.

Note

When you promote the Label mode active choice parameter to a mask, the Variant control mode is disabled. While promoting Label mode active choice parameter to a mask in a nested model, ensure that you promote Label mode active choice parameter to the immediate parent Variant Subsystem block mask.

If the block is in Expression mode while promoting Label mode active choice parameter to mask, you can change the Variant control mode to Label by changing the promoted Label mode active choice parameter from the Mask dialog box.
If the block is in Label mode while promoting Label mode active choice parameter to mask, you cannot change the Variant control mode to Expression mode.

For information about promoting parameters to mask, see Promote Parameter to Mask.

`Variant choices (table of variant systems)` — Table of variant choices, variant controls, and conditions
empty table (default)

The table has a row for each Variant system contained in the Variant Subsystem. If there are no Variant systems, the table is empty.

You can use buttons to the left of the Variant choices table to modify the elements in the table.

To...	Click...
Create and add a new subsystem choice: Place a new Subsystem Variant choice in the table and create a Subsystem block in the Variant Subsystem block diagram.
Create and add a new model variant choice: Place a new Model Variant choice in the table and create a Model block in the Variant Subsystem block.
Create/Edit selected variant object: Create a `Simulink.Variant` object in the global workspace and open the `Simulink.Variant` object parameter dialog box to specify the Variant Condition.
Open selected variant choice block: Open the Subsystem block diagram for the selected row in the Variant choices table.
Refresh dialog information from Variant Subsystem contents: Update the Variant choices table according to the Variant system and values of the Variant control in the global workspace.

`Name (read-only)` — Variant system name
`''` (default) | name of Subsystem or Model block contained in the Variant Subsystem

This read-only field is based on the Variant system name. To add a Subsystem Variant choice, click . To add a Model Variant choice, click .

`Variant control expression` — Variant control in global workspace
`Variant` (default) | boolean condition expression | a Simulink.Variant object representing a boolean condition expression | a Simulink.Parameter object (required for code generation) | enum

To enter a Variant name, double-click a Variant control cell in a new row and type in the Variant control expression.

To enter non-numeric Variant control values, use enumerated data. For information about using enumerated data, see Use Enumerated Data in Simulink Models

Programmatic Use

Structure field: Represented by the read-only variant.Name field in the Variant parameter structure

Type: character vector

Value: Variant control that is associated with the Variant choice

Default: 'variant'

`Condition (read-only)` — Condition for Variant controls
`''` (default)

This read-only field is based on the condition for the associated Variant control in the global workspace. Create or change a Variant condition in the Simulink.Variant parameter dialog box or in the global workspace.

`Label mode active choice` — Name of Active choice if Label mode is selected
`Choice_1` (default) | `on`

When you select the Variant control mode to Label, the Label mode active choice option is available. You can select an active Variant choice from Label mode active choice options. You can also right-click the badge on the Variant Subsystem block and select Label Mode Active Choice.

For Label mode active choice option, the Variant control need not be a Boolean condition expression or a Simulink.Variant object. Variant controls that start with a % symbol are ignored.

Note

Label mode active choice option is not available in Expression mode.

Dependencies

To enable this parameter, select Label option from Variant control mode parameter.

Programmatic Use

Parameter: LabelModeActivechoice

Type: character vector

Value: if no Label mode active choice is specified, the value is empty. If Label mode active choice is specified, the value is the name of the Label mode active choice.

Default: ''

`Allow zero active variant controls` — Simulate model without using active Variant
`off` (default) | `on`

To simulate a model (containing a Variant system) without an active Variant choice, select the Allow zero active variant controls option. When you select this option and if there is no active Variant choice, Simulink disables all the blocks connected to the input and output stream of Variant Subsystem block. The disabled blocks are ignored from update diagram or simulation.

If you do not select this option, Simulink generates an error when there is no active Variant choice.

Dependencies

The (default) option of Variant is not selected
Expression option from Variant control mode is selected.

Programmatic Use

Parameter: AllowZeroVariantControls

Type: character vector

Value: 'off' | 'on'

Default: 'off'

`Analyze all choices during update diagram and generate preprocessor conditionals` — Generate preprocessor conditionals
`off` (default) | `on`

When generating code for an ERT target, this parameter determines whether Variant choices are enclosed within C preprocessor conditional statements (#if).

When you select this option, Simulink analyzes all Variant choices during an update diagram or simulation. This analysis provides early validation of the code generation readiness of all Variant choices.

When you select this option, the Variant badge changes.

Dependencies

The check box is available for generating only ERT targets.
Expression option from Variant control mode is selected.

Programmatic Use

Parameter: GeneratePreprocessorConditionals

Type: character vector

Value: 'off' | 'on'

Default: 'off'

`Propagate conditions outside of variant subsystem` — Propagate Variant conditions outside of Variant Subsystem block
`off` (default) | `on`

When you select this option, Simulink propagates the Variant conditions outside of the Variant Subsystem block to determine which components of the model are active during simulation.

When you select this option, the Variant badge indicates the change.

Programmatic Use

Parameter: PropagateVariantConditions

Type: character vector

Value: 'off' | 'on'

Default: 'off'

Model Examples

Variant Subsystems

This model illustrates Simulink® variant subsystems. Variant subsystems let you provide multiple implementations for a subsystem where only one implementation is active during simulation. You can programmatically swap out the active implementation and replace it with one of the other implementations without modifying the model.

Open Model

Block Characteristics

Data Types	`Boolean^[a]` \| `bus^[a]` \| `double^[a]` \| `enumerated^[a]` \| `fixed point^[a]` \| `integer^[a]` \| `single^[a]` \| `string^[a]`
Direct Feedthrough	`no`
Multidimensional Signals	`limited^[a]`
Variable-Size Signals	`limited^[a]`
Zero-Crossing Detection	`no`
^[a] Actual data type or capability support depends on block implementation.

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

Actual data type or capability support depends on block implementation.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic. Actual data type or capability support depends on block implementation.

HDL Architecture

Architecture Description

Module (default) Generate code for the subsystem and the blocks within the subsystem. HDL Coder generates code for only the active variant.

Architecture	Description
`Module` (default)	Generate code for the subsystem and the blocks within the subsystem. HDL Coder generates code for only the active variant.
`BlackBox`	Generate a black-box interface. That is, the generated HDL code includes only the input/output port definitions for the subsystem. In this way, you can use a subsystem in your model to generate an interface to existing manually written HDL code. The black-box interface generated for subsystems is similar to the interface generated for Model blocks, but without generation of clock signals.
`No HDL`	Remove the subsystem from the generated code. You can use the subsystem in simulation but treat it as a “no-op” in the HDL code.

BlackBox

Generate a black-box interface. That is, the generated HDL code includes only the input/output port definitions for the subsystem. In this way, you can use a subsystem in your model to generate an interface to existing manually written HDL code.

The black-box interface generated for subsystems is similar to the interface generated for Model blocks, but without generation of clock signals.

No HDL

Remove the subsystem from the generated code. You can use the subsystem in simulation but treat it as a “no-op” in the HDL code.

Black Box Interface Customization

For the BlackBox architecture, you can customize port names and set attributes of the external component interface. See Customize Black Box or HDL Cosimulation Interface (HDL Coder).

HDL Block Properties

General
AdaptivePipelining	Automatic pipeline insertion based on the synthesis tool, target frequency, and multiplier word-lengths. The default is `inherit`. See also AdaptivePipelining (HDL Coder).
BalanceDelays	Detects introduction of new delays along one path and inserts matching delays on the other paths. The default is `inherit`. See also BalanceDelays (HDL Coder).
ClockRatePipelining	Insert pipeline registers at a faster clock rate instead of the slower data rate. The default is `inherit`. See also ClockRatePipelining (HDL Coder).
ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is `0`. For more details, see ConstrainedOutputPipeline (HDL Coder).
DistributedPipelining	Pipeline register distribution, or register retiming. The default is `off`. See also DistributedPipelining (HDL Coder).
DSPStyle	Synthesis attributes for multiplier mapping. The default is `none`. See also DSPStyle (HDL Coder).
FlattenHierarchy	Remove subsystem hierarchy from generated HDL code. The default is `inherit`. See also FlattenHierarchy (HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see InputPipeline (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see OutputPipeline (HDL Coder).
SharingFactor	Number of functionally equivalent resources to map to a single shared resource. The default is 0. See also Resource Sharing (HDL Coder).
StreamingFactor	Number of parallel data paths, or vectors, that are time multiplexed to transform into serial, scalar data paths. The default is 0, which implements fully parallel data paths. See also Streaming (HDL Coder).

Target Specification

This block cannot be the DUT, so the block property settings in the Target Specification tab are ignored.

Restrictions

The DUT cannot be a Variant Subsystem.

Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.

Actual data type or capability support depends on block implementation.

Documentation

Variant Subsystem, Variant Model

Description

Note

Ports

Input

In_1 — Input port corresponding to root-level Inport blocks contained in Variant Subsystem same data types accepted by Inport blocks

Output

Out_1 — Output port corresponding to root-level Outport blocks contained in Variant Subsystem same data types accepted by Outport blocks

Parameters

Variant control mode — Name of the Variant control mode Expression (default) | Label

Note

Variant choices (table of variant systems) — Table of variant choices, variant controls, and conditions empty table (default)

Name (read-only) — Variant system name '' (default) | name of Subsystem or Model block contained in the Variant Subsystem

Variant control expression — Variant control in global workspace Variant (default) | boolean condition expression | a Simulink.Variant object representing a boolean condition expression | a Simulink.Parameter object (required for code generation) | enum

Programmatic Use

Condition (read-only) — Condition for Variant controls '' (default)

Label mode active choice — Name of Active choice if Label mode is selected Choice_1 (default) | on

Note

Dependencies

Programmatic Use

Allow zero active variant controls — Simulate model without using active Variant off (default) | on

Dependencies

Programmatic Use

Analyze all choices during update diagram and generate preprocessor conditionals — Generate preprocessor conditionals off (default) | on

Dependencies

Programmatic Use

Propagate conditions outside of variant subsystem — Propagate Variant conditions outside of Variant Subsystem block off (default) | on

Programmatic Use

Model Examples

Variant Subsystems

Block Characteristics

Extended Capabilities

C/C++ Code Generation Generate C and C++ code using Simulink® Coder™.

HDL Code Generation Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

HDL Architecture

Black Box Interface Customization

HDL Block Properties

Restrictions

Fixed-Point Conversion Design and simulate fixed-point systems using Fixed-Point Designer™.

See Also

Topics

Introduced in R2010b

Simulink Documentation

Support

`In_1` — Input port corresponding to root-level Inport blocks contained in Variant Subsystem
same data types accepted by Inport blocks

`Out_1` — Output port corresponding to root-level Outport blocks contained in Variant Subsystem
same data types accepted by Outport blocks

`Variant control mode` — Name of the Variant control mode
`Expression` (default) | `Label`

`Variant choices (table of variant systems)` — Table of variant choices, variant controls, and conditions
empty table (default)

`Name (read-only)` — Variant system name
`''` (default) | name of Subsystem or Model block contained in the Variant Subsystem

`Variant control expression` — Variant control in global workspace
`Variant` (default) | boolean condition expression | a Simulink.Variant object representing a boolean condition expression | a Simulink.Parameter object (required for code generation) | enum

`Condition (read-only)` — Condition for Variant controls
`''` (default)

`Label mode active choice` — Name of Active choice if Label mode is selected
`Choice_1` (default) | `on`

`Allow zero active variant controls` — Simulate model without using active Variant
`off` (default) | `on`

`Analyze all choices during update diagram and generate preprocessor conditionals` — Generate preprocessor conditionals
`off` (default) | `on`

`Propagate conditions outside of variant subsystem` — Propagate Variant conditions outside of Variant Subsystem block
`off` (default) | `on`

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.