Actual code generation support depends on block implementation.
HDL Coder™ provides additional configuration options that affect HDL
implementation and synthesized logic.
You can define a System
object and use it in a MATLAB System block for HDL code
generation.
Tunable Parameter Support
HDL Coder supports tunable parameters with the following data types:
Numeric
Fixed point
Character
Logical
When using tunable parameters with the MATLAB System block, the
tunable parameter should be a Simulink.Parameter object with the
StorageClass
set to
ExportedGlobal
.
For
details, see
Generate DUT Ports for Tunable Parameters (HDL Coder).
HDL Architecture
This block has a single, default HDL architecture.
HDL Block Properties
If you use a predefined System
object, the HDL block properties available are the same as the properties
available for the corresponding block.
By default, the following HDL block properties are available.
ConstMultiplierOptimization | Canonical signed digit (CSD) or factored CSD optimization. The
default is none . See also ConstMultiplierOptimization (HDL Coder).
|
ConstrainedOutputPipeline | Number of registers to place at
the outputs by moving existing delays within your design. Distributed
pipelining does not redistribute these registers. The default is
0 . For more details, see ConstrainedOutputPipeline (HDL Coder).
|
DistributedPipelining | Pipeline register distribution, or register retiming. The default
is off . See also DistributedPipelining (HDL Coder).
|
InputPipeline | Number of input pipeline stages
to insert in the generated code. Distributed pipelining and constrained
output pipelining can move these registers. The default is
0 . For more details, see InputPipeline (HDL Coder).
|
LoopOptimization | Unroll, stream, or do not optimize loops. The default is none .
See also LoopOptimization (HDL Coder).
|
MapPersistentVarsToRAM | Map persistent arrays to RAM. The default is off .
See also MapPersistentVarsToRAM (HDL Coder).
|
OutputPipeline | Number of output pipeline stages
to insert in the generated code. Distributed pipelining and constrained
output pipelining can move these registers. The default is
0 . For more details, see OutputPipeline (HDL Coder).
|
ResetType | Suppress reset logic generation. The default is default ,
which generates reset logic. See also ResetType (HDL Coder).
|
SharingFactor | Number of functionally equivalent resources to map to a single
shared resource. The default is 0. See also Resource Sharing (HDL Coder).
|
VariablesToPipeline | Insert a pipeline register at the output of the specified MATLAB variable
or variables. Specify the list of variables as a character vector,
with spaces separating the variables.
|
Actual data type support depends on block implementation.