This example shows how to simulate and generate code for asynchronous events on a real-time multitasking system.
Open the example model rtwdemo_async_mdlreftop.
Data transfers occur between one reading task and one writing task.
A read or write operation on a byte-sized variable is atomic.
When two tasks interact, only one can preempt the other.
For periodic tasks, the task with the faster rate has higher priority than the task with the slower rate. The task with the faster rate preempts the tasks with slower rates.
Tasks run on a single processor. Time slicing is not allowed.
Processes do not crash and restart, especially while data is being transferred between tasks.
Simulate the model. By default, the model is configured to show sample times in different colors. Discrete sample times for input and output appear red and green, respectively. Constants are magenta. Asynchronous interrupts are purple. The Rate Transition Blocks, which are hybrid (input and output sample times can differ), appear yellow.
Generate code and a code generation report for the model. Async Interrupt block and Task Sync block generated code is for the example RTOS (VxWorks). However, you can modify the blocks to generate code for another run-time environment.
1. Create a temporary folder for the build and inspection process.
2. Build the model.
Open the generated source file rtwdemo_async_mdlreftop.c. The initialization code connects and enables ISR isr_num1_vec192 for interrupt 1 and ISR isr_num2_vec193 for interrupt 2.
In the generated source file rtwdemo_async_mdlreftop.c, review the code for ISRs isr_num1_vec192 and isr_num2_vec293. Each ISR:
Disables interrupts.
Saves floating-point context.
Calls the code generated for the subsystem connected to the referenced model Inport block that receives the interrupt.
Restores floating-point context.
Reenables interrupts.
The Task Sync block generates the following termination code.
Load Data to Root-Level Input Ports (Simulink)