Remove Redundant Logic

Components that do not contribute to the output in the design are removed during HDL code generation. Examples include:

HDL Coder evaluates the constant conditional values available at compile time. This simplifies the design.

To illustrate how this optimization simplifies your design:

1. Open the model hdlcoder_remove_redundant_logic and then open the DUT block.

open_system('hdlcoder_remove_redundant_logic.slx')
set_param('hdlcoder_remove_redundant_logic', 'SimulationCommand', 'update');

2. Open the DUT Subsystem block.

open_system('hdlcoder_remove_redundant_logic/DUT')

3. To generate HDL code for the design, at the MATLAB® command prompt, enter:

makehdl('hdlcoder_remove_redundant_logic/DUT')

4. Open the generated model. Double-click the DUT Subsystem.

HDL Coder™ evaluated the switch condition at compile time to pass the input from Subsystem_2 to the output, and eliminated Subsystem_1 input branch. In this example, there is no active output generated from the EnabledSubsystem_1 block. The EnabledSubsystem_1 block is removed during HDL code generation.

Removing redundant logic reduces the code size and avoids potential synthesis failures with downstream tools when you deploy the generated code onto a target platform. This optimization improves the performance of your design on the target hardware.

Optimize Unconnected Ports

During HDL code generation, the unconnected ports from the generated code are removed without removing ports from top-level DUT models or subsystems. This optimization includes removing unconnected vector and scalar ports, bus element ports, and bus ports. Removing unconnected ports improves the readability of the generated VHDL/Verilog code and reduces code size and area usage. The reduction avoids synthesis failure caused by unused ports in the HDL Coder™ generated VHDL/Verilog code.

To illustrate how unconnected ports are removed from a subsystem during HDL code generation:

1. Open the model hdlcoder_RemoveUnconnectedPorts containing bus element ports and a port connected to an inactive output.

open_system('hdlcoder_RemoveUnconnectedPorts.slx')
set_param('hdlcoder_RemoveUnconnectedPorts', 'SimulationCommand', 'update');

2. Open the dut Subsystem block.

open_system('hdlcoder_RemoveUnconnectedPorts/dut')

3. Open the mid_Subsystem block. The mid_Subsystem contains the bus element ports. One of the output signals is connected to a Terminator block.

open_system('hdlcoder_RemoveUnconnectedPorts/dut/mid_Subsystem')

4. To generate HDL code for the design, at the MATLAB® command prompt, enter:

makehdl('hdlcoder_RemoveUnconnectedPorts/dut')

The generated code mid_Subsystem.v shows the code with the unconnected port optimization. Here, the unconnected ports are removed during HDL code generation.

Following is an example of code with and without the unconnected port optimization.

Note: Removing redundant logic and the unconnected port optimizations do not affect traceability support.

Limitations

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