Terminate Unconnected Block Outputs and Usage of Commenting Blocks

You can follow these guidelines as recommended modeling practices such as making sure that block outputs are terminated and how you can comment out blocks for HDL code generation.

Each guideline has a severity level that indicates the level of compliance requirements. To learn more, see HDL Modeling Guidelines Severity Levels.

Terminate Unconnected Block Outputs

Open Script

Guideline ID

1.1.9

Severity

Mandatory

Description

If you generate HDL code for a Subsystem that has unconnected output ports, HDL Coder™ generates an error. For output ports that are not connected to downstream logic, connect them to a Terminator block.

This model illustrates a DUT0 Subsystem that has an unconnected output port Out2.

open_system('hdlcoder_terminateout')

If you generate HDL code for this Subsystem, HDL Coder™ generates this error:

error in validation model generation: Failed to find source for outport 2 on 'DUT0' Please create a fully connected subsystem when generating the cosimulation model.

close_system('hdlcoder_terminateout')

You can use the addterms function to add Terminator blocks to unconnected ports in your model.

load_system('hdlcoder_terminateout')
addterms('hdlcoder_terminateout')
open_system('hdlcoder_terminateout')

Using Comment Out and Comment Through of Blocks

Open Script

Guideline ID

1.1.10

Severity

Mandatory

Description

HDL Coder™ does not support code generation for a block or blocks that you comment through.

This model illustrates two Subsystems DUT_CommentOut and Dut_CommentThrough.

open_system('hdlcoder_comment_through_out')

The Dut_CommentThrough Subsystem contains a Subsystem that is commented through. HDL Coder™ generates an error for this Subsystem when generating code. In addition, the code generator does not support comment through for DUT input in testbench.

open_system('hdlcoder_comment_through_out/DUT_CommentThrough/Generated')

The code generator supports blocks that are commented out when the output signals are unused. The generated code assigns a constant value of 0 to the signal at the output. The Dut_CommentOut Subsystem contains two subsystems that are commented out.

open_system('hdlcoder_comment_through_out/DUT_CommentOut')

When you generate code for Dut_CommentOut, HDL Coder ignores these subsystems. The Generated Subsystem has blocks that are commented out and outputs a zero value.

You see this VHDL code generated for this Subsystem which indicates a constant zero value assigned to Out1.

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;

ENTITY Generated IS
  PORT( Out1                              :   OUT   std_logic_vector(15 DOWNTO 0)  -- sfix16_En6
        );
END Generated;


ARCHITECTURE rtl OF Generated IS

  -- Signals
  SIGNAL TmpGroundAtData_Type_DuplicateInport1_out1 : signed(15 DOWNTO 0);  -- sfix16_En6

BEGIN
  -- Unsupported Block

  TmpGroundAtData_Type_DuplicateInport1_out1 <= to_signed(16#0000#, 16);

  Out1 <= std_logic_vector(TmpGroundAtData_Type_DuplicateInport1_out1);


END rtl;

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