Clock Rate Pipelining

This section contains parameters in the HDL Code Generation > Optimization > Pipelining tab of the Configuration Parameters dialog box. Using the parameters in this section, you can improve the timing of your design on the target device. Enable clock-rate pipelining and allow clock-rate pipelining at the DUT output ports to run the pipeline registers at a faster clock rate on the target FPGA device.

Clock-rate pipelining

If your design contains multicycle paths, use clock-rate pipelining to insert pipeline registers at a clock rate that is faster than the data rate. This optimization improves the clock frequency and reduces the area usage without introducing additional latency. Clock-rate pipelining does not affect existing design delays in your model. It is an alternative to using multicycle path constraints with your synthesis tool.

Settings

Default: On

On: Insert pipeline registers at the clock rate for multi-cycle paths.
Off: Insert pipeline registers at the data rate for multi-cycle paths.

Dependency

If you specify an Oversampling factor greater than one, make sure that you select the Clock-rate pipelining check box. Clock-rate pipelining identifies regions in your model that run at the same slow data rate and are delimited by Delay blocks or blocks that introduce a rate transition. The code generator converts these regions to the faster clock rate by introducing Repeat blocks at the input of the region and Rate Transition blocks at the output of the region.

Command-Line Information

Property: ClockRatePipelining

Type: character vector

Value: 'on' | 'off'

Default: 'on'

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

For example, you can use the ClockRatePipelining setting when you generate HDL code for the symmetric_fir subsystem inside the sfir_fixed model using either of these methods.

Pass the property as an argument to the makehdl function.

makehdl('sfir_fixed/symmetric_fir', ... 
        'ClockRatePipelining','on')

When you use hdlset_param, you can set the parameter on the model and then generate HDL code using makehdl.
```
hdlset_param('sfir_fixed','ClockRatePipelining','on')
makehdl('sfir_fixed/symmetric_fir')
```

Allow clock-rate pipelining of DUT output ports

For DUT output ports, insert pipeline registers at the clock rate instead of the data rate.

Settings

Default: Off

On: At DUT output ports, insert pipeline registers at clock rate.
Off: At DUT output ports, insert pipeline registers at data rate.

Dependency

When you specify this parameter, make sure that you select the Clock-rate pipelining check box.

Command-Line Information

Property: ClockRatePipelineOutputPorts

Type: character vector

Value: 'on' | 'off'

Default: 'off'

To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.

For example, you can use the ClockRatePipelineOutputPorts setting when you generate HDL code for the symmetric_fir subsystem inside the sfir_fixed model using either of these methods.

Pass the property as an argument to the makehdl function.

makehdl('sfir_fixed/symmetric_fir', ... 
        'ClockRatePipelineOutputPorts','on')

When you use hdlset_param, you can set the parameter on the model and then generate HDL code using makehdl.
```
hdlset_param('sfir_fixed','ClockRatePipelineOutputPorts','on')
makehdl('sfir_fixed/symmetric_fir')
```

Documentation