Clock Enable and Reset Input Signals
Force clock enable
Specify whether the test bench forces clock enable input signals.
Settings
Default: On
On The test bench forces the clock enable input signals to active-high (1) or active-low (0), depending on the setting of the clock enable input value.
OffA user-defined external source forces the clock enable input signals.
Dependencies
This property enables the Clock enable delay (in clock cycles) option.
This option is disabled if you select the entire model. Select the DUT instead for Generate HDL for setting.
Command-Line Information
Property:
ForceClockEnable |
| Type: character vector |
Value:
'on' | 'off' |
Default:
'on' |
To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.
See Also
Clock enable delay (in clock cycles)
Define elapsed time (in clock cycles) between deassertion of reset and assertion of clock enable.
Settings
Default: 1
The Clock enable delay (in clock cycles) property defines the number of clock cycles elapsed between the time the reset signal is deasserted and the time the clock enable signal is first asserted. In the figure below, the reset signal (active-high) deasserts after 2 clock cycles and the clock enable asserts after a clock enable delay of 1 cycle (the default).
Dependency
This parameter is enabled when Force clock enable is selected.
Command-Line Information
Property:
TestBenchClockEnableDelay |
| Type: integer |
| Default: 1 |
To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.
See Also
Force reset
Specify whether the test bench forces reset input signals.
Settings
Default: On
- On
The test bench forces the reset input signals.
- Off
A user-defined external source forces the reset input signals.
Tips
If you select this option, you can use the Hold time option to control the timing of a reset.
Dependency
This option is disabled if you select the entire model. Select the DUT instead for Generate HDL for setting.
Command-Line Information
Property:
ForceReset |
| Type: character vector |
Value:
'on' | 'off' |
Default:
'on' |
To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.
See Also
Reset length (in clock cycles)
Define length of time (in clock cycles) during which reset is asserted.
Settings
Default: 2
The Reset length (in clock cycles) property defines the number of clock cycles during which reset is asserted. Reset length (in clock cycles) must be an integer greater than or equal to 0. The following figure illustrates the default case, in which the reset signal (active-high) is asserted for 2 clock cycles.
Dependency
This parameter is enabled when Force reset is selected.
Command-Line Information
Property:
Resetlength |
| Type: integer |
| Default: 2 |
To set this property, use hdlset_param or makehdl. To view the property value, use hdlget_param.